module axi_frv_core_wrapper (
    input                   pd_rst          ,
    input                   pd_wr           ,
    input [31:0]            pd_wdata        ,
    input [8:0]  pd_waddr        ,
    // ==========================================================================
    // Interrupt Interface
    input                   plic_int_vld    ,
    input                   clic_int_vld    ,  
    Axi4LiteIf.master       master
);

frv_core_top _frv_core_top(
.clk                    (master.clk     ),
.rst_n                  (master.rst_n   ),
.pd_rst                 (pd_rst      ),
.pd_wr                  (pd_wr       ),
.pd_wdata               (pd_wdata    ),
.pd_waddr               (pd_waddr    ),
.plic_int_vld           (plic_int_vld),
.clic_int_vld           (clic_int_vld),
.dev_awtid              (),
.dev_awaddr             (master.awaddr  ),
.dev_awprot             (master.awprot  ),
.dev_awvalid            (master.awvalid ), 
.dev_awready            (master.awready ),
.dev_wtid               (), 
.dev_wdata              (master.wdata   ),
.dev_wstrb              (master.wstrb   ),
.dev_wvalid             (master.wvalid  ),
.dev_wready             (master.wready  ),
.dev_btid               (),
.dev_bresp              (master.bresp   ),
.dev_bvalid             (master.bvalid  ),
.dev_bready             (master.bready  ),
.dev_artid              (),
.dev_araddr             (master.araddr  ),
.dev_arprot             (master.arprot  ),
.dev_arvalid            (master.arvalid ),
.dev_arready            (master.arready ),
.dev_rtid               (),
.dev_rdata              (master.rdata   ),
.dev_rresp              (master.rresp   ),
.dev_rvalid             (master.rvalid  ),
.dev_rready             (master.rready  )     
);


endmodule
